Circuit Design for Low-Power High-Speed VLSI Processor in 0.5V Generation

In the past 30 years, the semiconductor industry has been expanded drastically by the downsizing of the transistors. The progress of the downsizing, however, has increased the chip power. As the battery-powered products, like mobile computers and mobile phones, become popular, the low-power design becomes the one of the most important issues of the LSI design. On the other hand, high-performance design is also a crucial issue since main-stream supply voltage, VDD, will be scaled down to below 0.5V in the coming years. In order to achieve the low-power and high-performance at a same time, not only the device improvement but also the new low-power circuit schemes and new low-power architecture are needed. First, the short-circuit power component and the voltage dependence on the capacitance, which have not been fully investigated, are discussed. Then, the closed-form formulas are presented for optimum supply voltage and threshold voltage that minimize the power dissipation when technology parameters and required speed are given. The formulas take into account the short-channel effects, the temperature variation and VTH fluctuation. From the calculation using these formulas, it is shown that a simple guideline for power optimization is to set the ratio of the maximum leakage power to the total power around 30%. Extending the analysis, the future VLSI design trend is discussed based on ITRS. The optimum target VTH is almost constant at 0.2V over generations. The proposed scenario shows that more number of MOSFET is consumed in the memory blocks than the logic blocks in the future. Long wires, like signal buses, become dominant performance limiter in high-performance VLSI’s. In this study, closed-form formulas for optimum buffer insertion where the junction capacitance is taken into account are proposed. Using these formulas, the optimum interconnect delay and power comparison among bulk, silicon-on-insulator (SOI) and the double-gate structure are discussed. MOSFET with small junction capacitance, like SOI, can suppress both the interconnect delay and power by 15% compared with MOSFET where the junction capacitance is equal to the gate capacitance, like conventional bulk MOSFET. Based on the above-mentioned analysis, a new buffer insertion scheme for bi-directional buses, namely dual-rail bus (DRB) scheme, which does not have noise problems, and a high-speed buffer insertion scheme for uni-directional buses, namely staggered firing bus (SFB) scheme, are proposed and measured. When 0.07μm design rule is used, DRB scheme can improve the performance of bi-directional buses by an order of magnitude and SFB scheme can suppress the delay of uni-directional buses by about 20% at 0.18μm generation and beyond. If we use SFB scheme instead of conventional uni-directional buses, 27% power reduction can be achieved while the performance of SFB is the same as that of conventional buses. Finally, new active leakage power reduction schemes are proposed. In order to suppress the leakage power, it is effective to increase the threshold voltage. In the proposed schemes, the threshold voltage, VTH, is dynamically controlled through software depending on a workload. The dynamical control system consists of the cooperation between software and hardware. There are two techniques to control the threshold voltage dynamically. The first one is controlling the back-gate bias of the transistors, which is called VTH-hopping. The VTH-hopping scheme can achieve 82% power saving compared with the fixed low-VTH circuits in 0.5V supply voltage regime for multimedia applications. A small-scale RISC processor with VTH-hopping and the positive back-gate biased scheme is fabricated. Based on the measured data, performance evaluation is conducted using MPEG-4 video coding. The result shows that 86% power saving can be achieved by using VTH-hopping compared with the fixed positive back-bias scheme. The other technique to control the threshold voltage is controlling VDD. This technique utilizes the Drain Induced Barrier Lowering (DIBL). If the drain-source voltage, that is, the supply voltage is lowered, the subthreshold leakage current can be suppressed since the threshold voltage increases by the DIBL effect. In order to verify the effectiveness of DIBL-hopping, MPEG-4 encoding is simulated based on the measured results. The result shows that 75% power reduction can be achieved compared with the fixed VDD scheme. These schemes are effective for the design of the future low-voltage, low-power CMOS VLSI’s.